Regviz

Silicon Labs /MGM210PA32JIA /CMU_S /WDOG1CLKCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as WDOG1CLKCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/BGM210LA22JNF/CMU_NS/WDOG1CLKCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKSEL

Description

No Description

Fields

CLKSEL

Clock Select

1 (LFRCO): LFRCO is clocking WDOG1CLK

2 (LFXO): LFXO is clocking WDOG1CLK

3 (ULFRCO): ULFRCO is clocking WDOG1CLK

4 (HCLKDIV1024): HCLKDIV1024 is clocking WDOG1CLK

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data